1. Technical Field
The present invention relates to a generator circuit of a reference voltage in memory devices with non-volatile cells matrix.
The invention also relates to a method for generating such a reference voltage in memory devices with a non-volatile cell matrix.
The invention particularly, but not exclusively, relates to a circuit for generating a reference voltage in memory devices of the EEPROM type and the following description is made with reference to this field of application for convenience of explanation only.
2. Description of the Related Art
As it is well known, a memory semiconductor device comprises a plurality of non-volatile memory cells, such as for example EEPROM cells, which are usually integrated on a substrate of semiconductor material and ordered in rows and columns in a cells matrix structure. In such a memory device, the element for the information storage, i.e., the single cell, is a MOS transistor of the floating gate type and the amount of charge contained in such floating gate defines the logic state or level of the corresponding single cell. In particular, the floating gate of each memory cell is electrically insulated from the floating gate of each adjacent cell.
Such memory semiconductor device further comprises suitable circuit blocks integrated on the substrate and connected to the matrix of memory cells for allowing to program, to read and to erase, in a selective way, these cells.
Lately, a remarkable development has been shown by those applications, which require the use of memory devices with matrixes of electrically erasable cells, such as memory cells of the EEPROM type.
In fact, EEPROM cells show the peculiarity of being erased in parallel single word by single word and programmed single bit by single bit, i.e., single cell by single cell. Moreover, these EEPROM memory cells have the peculiarity of providing an extremely reduced current consumption both during the reading operation and during the modification operation (erasing or programming) of the content of the cells themselves.
For these peculiarities, memory devices with EEPROM cells are nowadays widespread in several applications and used for example for the realization of the more and more widely used smart cards.
In particular, the request for more and more compact applications has pushed the research to the reduction of the physical dimensions of the memory devices and in particular of the memory cells of the matrix. The physical dimensions of the cells nowadays reached at the end of the productive process however make it exacting and complex, in particular, the erasing operation of the memory cell, operation requested for bringing the cells back to an original or erased state, i.e., to a condition of a virgin cell through elimination of the electric charges contained in the floating gate region.
In these memory devices with reduced dimensions, for discriminating a programmed state from an erased state of the memory cells, it is known to generate, by means of a suitable voltage generator circuit, a reference voltage which is applied to a gate electrode of the matrix and is used for biasing, at a desired value, the memory cells.
Some known solutions, used for example in matrixes of memory cells of the “Flash” EEPROM type, provide to generate such a reference voltage by using suitable algorithms suitable for defining the value thereof.
These solutions however show some drawbacks, the use of algorithms requiring a greater waste from the viewpoint of the circuit, i.e., occupied area, and also a greater waste from the operative viewpoint. In fact, an additional operation is requested on the matrix cells, called “testing” operation, which implies, in most applications, an excessive lengthening of the erasing times.
Alternatively, it is known to use a generator circuit of a control voltage to be applied to the control gate of the memory cells and commonly indicated as control gate voltage, whose principle scheme is shown in FIG. 1. This circuit 1 comprises one or more reference EEPROM cells suitably biased and suitable for driving at the output a certain number of memory cells of a device connected thereto. The reference cells engaged in the voltage generator circuit 1 are of the UV type, i.e., of the type wherein it is possible to erase—by means of the ultraviolet rays—the electric charges stored in the floating gate region of each cell.
In the schematically shown circuit 1, by simplicity of illustration, a single reference UV cell 2 is highlighted which shows a source terminal 3 connected to a voltage reference V1, in particular a ground Gnd, a drain terminal 4 and a gate terminal 5 connected to an output terminal O1 of the circuit 1.
This circuit 1 also comprises a emulation block 6 of a sense amplifier, substantially a current-voltage converter, which comprises a first input terminal connected to a generator 7 of a reference current Iref and a second input terminal connected to the drain terminal 4 of the reference UV cell 2. The emulation block 6 signals to a buffer 8 placed in cascade thereto that the reference current Iref of the generator 7 and the current generated by the reference UV cell 2 are identical.
The buffer 8, which can be realized for example by an operational amplifier, compares the voltages at the input and if they are identical it supplies the output terminal O1 of the circuit 1 with a reference voltage Vcg.
Suitably, the output terminal O1 of the circuit 1 is connected to the gate electrode of the memory cells of the matrix and the reference voltage Vcg generated on the output terminal O1 of the circuit allows to bias these cells.
Further, the circuit 1 provides a feedback connection between its own output terminal O1 and the gate terminal 5 of the reference UV cell 2 by basing it at the reference voltage Vcg.
The circuit 1 also comprises an output stage comprising a filter capacitor 10, connected between the output terminal O1 and the ground voltage reference V1. In particular, this filter capacitor 10 is suitable for reducing the possible “ripple” voltage at the output terminal O1 of the circuit 1 and for increasing its capacity of driving successive stages connected to the output terminal O1. The filter capacitor 10 is suitably sized on the basis of the number of cells connected to the gate electrode of the matrix.
The known circuit just described, although meeting the aim, is not however exempt from drawbacks. In fact, the filter capacitor 10 of its output stage, for ensuring the reduction of the “ripple” voltage on the output terminal O1, can reach high values occupying an excessive silicon area. For example, in some cases, this capacitor can reach values in the order of some tens of picofarads.
Moreover, for a correct biasing of the memory cells of the matrix during a reading operation, it is necessary that the reference UV cells 2 of the circuit 1 are under the condition of a virgin cell at the end of the relative productive process.
Because of their reduced physical dimensions, current devices use a high dosage of UV rays for bringing the reference UV cells 2 to a virgin condition. This operation thus is particularly exacting, long and expensive and, in some cases, extremely reduced dimensions being present, risks not to be ensured anymore.